Arc Reactor Core

> initializing system interface...

Nitish Singh

Architecting hardware-software ecosystems.

Builder operating at the intersection of technology and system architecture.
I design, engineer, and scale end-to-end solutions — integrating logic into physical systems that scale beyond the screen.

₹30L+Vessel Scaled
10+Core Systems
🥇SIH Winner
Top 4Global Hardware

Selected Systems

[SYS-01] [DEPLOYED]

TechDeck Macropad

Firmware-to-Application Pipeline

Owned the complete design-to-deployment lifecycle for high-performance input hardware, integrating C++ firmware with a Python-based automation engine.

Architecture: C++ firmware serializing HID inputs into a background daemon for dynamic macro-profile mapping across OS layers.

Embedded Systems Python Daemon FDM Prototyping
[SYS-02] [IN DEVELOPMENT]

Smart Infra Hub

Unified Local-First Protocol

Engineered a localized orchestration layer for infrastructure, abstracting vendor telemetry into a unified, secure routing grid for automation relays.

Architecture: Distributed Linux services handling sub-socket networks to unify heterogeneous IoT nodes through a centralized gateway.

Network Architecture Computer Vision Python
[SYS-03] [ACTIVE]

WipeTech Secure

Low-Level Storage Mutator

Designed a cross-platform data pipeline that bypasses file-system abstractions to force sequential magnetic overwrite on physical platter allocations.

Architecture: Python-based block device interface overriding OS standard allocators to guarantee bit-level data non-persistence.

OS Internals Security Subsystems
[SYS-04] [ACTIVE]

RPi Home NAS

Headless Storage Array

Fault-tolerant attached storage node designed to enforce absolute data sovereignty over standard cloud backups. Multi-user partitioning directly mapped on ARM hardware.

Architecture: SMB/CIFS networking stacks mounted over physical Debian ext4 arrays for dynamic volume provisioning.

Debian Storage Topology Network Attached

Proof of Execution

💰

Venture Build

What: Scaled hardware venture to ₹30L+ revenue.
How: Owned the end-to-end supply chain and engineered a backend pipeline that optimized throughput by 25% under peak load.

🏆

SIH Victory

What: Winner - Internal Hackathon Protocol.
How: Engineered a storage-mutator protocol overriding standard OS platter allocators for guaranteed data non-persistence.

🥇

CDAC Summit

What: Rank 1 Technical Project Victoria.
How: Owned the prototype design cycle, blending architectural CAD topology with real-world FDM manufacturing constraints.

🌍

Global Hardware

What: Rank 4 overall out of 180+ international teams.
How: Integrated firmware, desktop telemetry, and 3D structural layouts to deploy the TechDeck Macropad at IHMMC.

Operating Experience

Founder / Lead Engineer

TechnologyHell Ongoing
  • Owned the engineering and business architecture for a hardware-focused venture, scaling to ₹30L+ annual revenue.
  • Engineered system-level hardware/firmware integrations using microcontroller logic and Python automation pipelines.
  • Architected Node.js + MongoDB infrastructure, reducing latency by 25% and ensuring high availability for order tracking.
  • Owned the end-to-end supply chain logistics, vendor negotiations, and technical inventory planning for consistent delivery.

President - SIT Ideathon 4.0

Siliguri Institute of Technology Ongoing
  • Owned high-level tournament execution for 100+ participants, coordinating technical judging and pitch orchestration.
  • Architected the evaluation framework for innovation-led prototypes, ensuring technical feasibility vs. business viability audits.
  • Managed stakeholder relations between industry partners and innovators to secure pilot-phase interest.

Business Associate + Coordinator

WebMarvel Past
  • Owned the technical delivery layer for enterprise projects, aligning technical execution with client business requirements.
  • Architected technical specification pipelines, reducing development iteration cycles by 30%.
  • Acted as the primary technical bridge between stakeholders and developers, resolving technical ambiguities in real-time.
  • Engineered streamlined delivery workflows and requirement pipelines, maintaining strict adherence to project SLAs.

Build Matrix

Core Infrastructure

Linux Kernels Sub-Socket Networking Hardware NAS Edge Cloudflare DNS

Application Layer

Python Daemons MERN Distribution Java OOP Services Vanilla DOM Rendering

Hardware Synthesis

Arduino / STM32 FDM Additive Manuf. PCB Rapid Prototyping Embedded C++

Engineering Tools

Blender Topography AutoCAD Schematics Git Telemetry

Product & Operations

Supply Chain Systems Product Lifecycle (PLM) Cost Optimization Vendor Coordination Customer Systems

System Design & Architecture

Modular Architecture Local-first Systems API Integration Data Flow Design Multi-layer System Thinking

Elite Achievements

ELITE 🏆

SIH Logic Champion

Rank 1 - Internal Subsystem Logic Hackathon. Engineered a storage-mutator protocol for OS-level data non-persistence.

GLOBAL 🌍

IHMMC Rank 4

Rank 4 / 180+ teams globally. Integrated firmware, desktop telemetry, and structural layouts for TechDeck deployments.

TECHNICAL 🥇

CDAC Technical Layer 1

Rank 1 - Additive Manufacturing Summit. Blended advanced CAD topology with real-world manufacturing constraints.

LEADERSHIP 🏆

Eureka! Winner

National Winner - SIT Ideathon 4.0. Architected the winning pitch orchestration and evaluation framework.

HARDWARE 🤖

Robotics Victor

Prototype victory at Vision to Venture (IIT Bombay). Designed hardware logic for functional robotic nodes.

STRATEGY 🧠

National Finalist

Top tiered execution in high-level Quizzing and Strategy tournaments at national orchestration levels.

SYS: NOW

Architecting a unified local-first Smart Infrastructure Hub — abstracting away vendor telemetry into a localized AI routing grid.

SYS: NEXT

Productizing infrastructure deployments into fully contained real-world hardware models spanning 10k+ nodes.

Let's build something real.